1. Field of the Invention
The present invention relates to a semiconductor device, and, more particularly, to a semiconductor device that has a metal thin-film resistor on a base insulating film.
2. Description of the Related Art
In analog integrated circuits, resistor devices are often employed as essential components. In recent years, attention has been drawn to resistors that are formed with metal thin films (hereinafter referred to as metal thin-film resistors), as the resistance of a metal thin-film resistor has low temperature dependency (or a small TCR). The materials for the metal thin-film resistors include chromium silicon (CrSi), nickel chromium (NiCr), tantalum nitrogen (TaN), chromium silicide (CrSi2), chromium silicide nitride (CrSiN) and chromium silicon oxide (CrSiO).
To satisfy the requirement for higher integrated analog circuits in a semiconductor device having metal thin-film resistors, each metal thin-film resistor is formed with a small thickness of 1000 Å (angstrom) so as to obtain higher sheet resistance.
Conventionally, there have been the following techniques for establishing electric connection with metal thin-film resistors:    1) The technique of directly connecting a metal wire to each metal thin-film resistor (disclosed in Japanese Laid-Open Patent Application No. 2002-124639, for example);    2) The technique of connecting a metal wire to each metal thin-film resistor via connecting holes that are formed in an interlayer insulating film that is formed after the formation of the metal thin-film resistors (disclosed in Japanese Laid-Open Patent Application No. 2002-261237 and Japanese Patent Publication No. 2699559, for example); and    3) The technique of connecting a metal wire to each metal thin-film resistor layer by connecting the metal wire to a barrier film that is formed on each thin-film resistor layer (disclosed in Japanese Patent Publication Nos. 2932940 and 3185677, for example).
In the following, the techniques 1)-3) of establishing electric connection with metal thin-film resistors are described.
Referring to FIG. 29, the technique 1) of forming a metal wire directly on each metal thin-film resistor is first described.
An interlayer insulating film 5 is formed on a wafer-type silicon substrate 1, after the formation of a device isolating oxide film 3 and a transistor (not shown). A metal thin-film resistor 101 is then formed on the interlayer insulating film 5. A wiring metal film is formed on the entire surface of the interlayer insulating film 5 including the metal thin-film resistor 101. The wiring metal film is patterned by a wet etching technique, so as to form metal wiring patterns 103.
In the general procedures for manufacturing a semiconductor device, a dry etching technique is employed for the etching of the wiring metal film. With the metal thin-film resistor 101 with a smaller thickness existing immediately below the wiring metal film, however, overetching is caused to etch the metal thin-film resistor 101 if a dry etching technique is used. Therefore, a dry etching technique should be avoided, and the metal wiring patterns 103 need to be formed by patterning the wiring metal film by a wet etching technique.
Referring now to FIG. 30, the technique 2) of connecting a metal wire to a metal thin-film resistor via connecting holes that are formed in an interlayer insulating film that is formed after the formation of the metal thin-film resistor is described.
After the formation of a device isolating oxide film 3, an interlayer insulating film 5, and a metal thin-film resistor 101 on a silicon substrate 1, a CVD (chemical vapor deposition) oxide film 105 that is to serve as an interlayer insulating film for the metal wire is formed on the interlayer insulating film 5 including the metal thin-film resistor 101. A resist pattern for forming the connecting holes for the connection with the metal wire is then formed on the CVD oxide film 105. The resist pattern has openings corresponding to both end portions of the metal thin-film resistor 101. With the resist pattern serving as a mask, the CVD oxide film 105 is selectively removed by a wet etching technique, thereby forming the connecting holes 107. After the removal of the resistor pattern, a wiring metal film that is made of AlSCu is formed on the CVD oxide film 105 including the inside of each connecting hole 107. The wiring metal film is patterned to form metal wiring patterns 109.
In the general procedures for manufacturing a semiconductor device, a dry etching technique is used to form the connecting holes 107. If the metal thin-film resistor 101 is thinner than 1000 Å, however, it is difficult to prevent the connecting holes 107 from penetrating the metal thin-film resistor 101. Therefore, the connecting holes 107 need to be formed by a wet etching technique.
Referring now to FIG. 31, the technique 3) of connecting a metal wire to a metal thin-film resistor layer by connecting the metal wire to a barrier film that is formed on the thin-film resistor layer is described.
After the formation of a device isolating oxide film 3, an interlayer insulating film 5, and a metal thin-film resistor 101 on a silicon substrate 1, a refractory metal film that is made of TiW or the like and is to serve as a barrier film for the metal wire is formed on the interlayer insulating film 5 including the metal thin-film resistor 101. A wiring metal film is further formed on the refractory metal film, and the wiring metal film is patterned by a dry etching technique to form metal wiring patterns 111. With the refractory metal film existing under the wiring metal film, the metal thin-film resistor 101 is not etched by a dry etching technique. With the metal wiring patterns 111 serving as a mask, the refractory metal film is selectively removed by a wet etching technique to form a refractory metal film pattern 113. Since the refractory metal film exists immediately above the metal thin-film resistor 101, it is difficult to pattern the refractory metal film by a dry etching technique.
FIG. 32 shows an example of use of metal thin-film resistors. In the example shown in FIG. 32, belt-like metal thin-film resistors 101 are arranged in parallel, and are connected in series with the metal wiring patterns 103. Although the reference numerals in FIG. 32 correspond to the reference numerals in FIG. 29, it is of course possible to arrange belt-like metal thin-film resistors 101 in parallel and connect the metal thin-film resistors 101 with the metal wiring patterns 109 or 111 in the conventional examples shown in FIGS. 30 and 31.
Also, a semiconductor integrated circuit device that is equipped with resistors formed on the uppermost wiring electrode via an insulating film and are connected to the uppermost wiring electrode has been disclosed (in Japanese Laid-Open Patent Application No. 58-148443, for example). This disclosure does not concern metal thin-film resistors.
Referring to FIGS. 33A and 33B, a case where such a structure is applied to metal thin-film resistors is described. FIG. 33A is a plan view, and FIG. 33B is a cross-sectional view, taken along the line X-X of FIG. 33A.
An interlayer insulating film 5 is formed on a silicon substrate 1 having a device isolating oxide film 3 formed thereon, and metal wiring patterns 115 are formed on the interlayer insulating film 5. A base insulating film 131 is formed on the entire surface of the interlayer insulating film 5 including the metal wiring patterns 115. Connecting holes 117 are then formed in the base insulating film 131 on the metal wiring patterns 115 by a photoengraving technique and a dry etching technique. A metal thin film for forming metal thin-film resistors are then formed on the entire surface of the base insulating film 131 including the formation regions of the connecting holes 117. The metal thin film is then patterned into predetermined shapes, so as to form metal thin-film resistors 101.
As shown in FIG. 33B, the lower surfaces of the metal thin-film resistors 101 are electrically connected to the metal wiring patterns 115 in the respective connecting holes 117.
As shown in FIG. 33A, the metal thin-film resistors 101 are connected in series via the metal wiring patterns 115.
Also, as a semiconductor device that is equipped with metal thin-film resistors, an integrated circuit that has metal thin-film resistors mounted on an insulating film of the semiconductor integrated circuit is disclosed (in Japanese Laid-Open Patent Application No. 61-100956, for example). In this structure, the contact between the metal thin-film resistors and the metal wires at the electrode portions of the metal thin-film resistors is located at least a part of the end surface and the upper surface of the end portions of each metal wire.
Referring now to FIGS. 34A and 34B, the technique of establishing contact between the metal thin-film resistors and the metal wires on at least a part of the end surface and the upper surface of the end portion of each metal wire is described. FIG. 34A is a plan view, and FIG. 34B is a cross-sectional view, taken along the line Y-Y of FIG. 34A.
An interlayer insulating film 5 is formed on a silicon substrate 1 having a device isolating oxide film 3 formed thereon, and metal wiring patterns 115 are formed on the interlayer insulating film 5. After a plasma nitride film 119 is formed on the entire surface of the interlayer insulating film 5 including the metal wiring patterns 115, the plasma nitride film 119 is partially removed to partially expose the end surface and the upper surface of the metal wiring patterns 115. A metal thin film for forming metal thin-film resistors is then deposited. The metal thin film is patterned to form metal thin-film resistors 101.
As shown in FIG. 34B, the lower surfaces of the metal thin-film resistors 101 are electrically connected to the upper surface and the side surface of the metal wiring patterns 115.
As shown in FIG. 34A, the metal thin-film resistors 101 are connected in series via the metal wiring patterns 115.
In the case where the lower surfaces of the metal thin-film resistors 101 are electrically connected to the metal wiring patterns 115 via the connecting holes 117, as shown in FIGS. 33A and 33B, the resistance of a metal thin-film resistor 101 is calculated by totaling the resistance of each metal thin-film resistor 101 between the connecting holes 117 including the side surfaces of the connecting holes 117 and the contact resistance between the metal thin-film resistors 101 at both ends and the metal wiring patterns 115.
In the structure shown in FIGS. 33A and 33B, however, a step portion is formed in the base insulating film 131 in the vicinity of the metal wiring patterns 115, due to the side surfaces of the metal wiring patterns 115. The step portion affects the line width of each metal thin-film resistor 101, resulting in an inaccurate resistance value of each metal thin-film resistor 101.
Also, as shown in FIGS. 34A and 34B, in the case where the upper surfaces of the metal thin-film resistors 101 are electrically connected to the upper surfaces and the side surfaces of the metal wiring patterns 115, the resistance of a metal thin-film resistor 101 is calculated by totaling the resistance of each metal thin-film resistor 101 between the metal wiring patterns 115 and the contact resistance between the metal thin-film resistors 101 at both ends and the metal wiring patterns 115.
In the structure shown in FIGS. 34A and 34B, however, a step portion is formed due to the side surfaces of the metal wiring patterns 115. The step portion affects the line width of each metal thin-film resistor 101 in the vicinity of the metal wiring patterns 115. As a result, a desired resistance value of each metal thin-film resistor 101 cannot be obtained in this structure, either.